Digital coherent optical receiver

ABSTRACT

A digital coherent optical receiver provided with a 90-degree optical hybrid circuit for detecting an in-phase signal and a quadrature signal of an input optical signal, includes first through fourth circuits. The first circuit calculates a square of a sum of the in-phase signal and the quadrature signal. The second circuit subtracts a squared value of the in-phase signal and a squared value of the quadrature signal from the calculation result of the first circuit. The third circuit detects a phase error of the 90-degree optical hybrid circuit based on the calculation result of the second circuit. The fourth circuit corrects at least one of the in-phase signal and the quadrature signal according to the phase error detected by the third circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of theprior Japanese Patent Application No. 2009-131343, filed on May 29,2009, the entire contents of which are incorporated herein by reference.

FIELD

The present invention relates to a digital coherent optical receiver.

BACKGROUND

Large-capacity optical communication systems have been promoted alongwith the spread of the Internet. For example, for a trunk line system,an optical transmitter and an optical receiver capable of transmittingsignals with 40 Gbit/s or more per wavelength are studied.

When a bit rate per wavelength is increased, an optical signal to noiseratio (OSNR) tolerance is degraded and the deterioration of signalquality due to waveform distortion caused by the chromatic distribution,polarization mode distribution, non-linear effect of the transmissionline, and the like increases. Therefore, a digital coherent receiverwith high OSNR tolerance and high waveform distortion tolerance has beenfocused on recently.

In the digital coherent receiving method, optical amplitude informationand phase information is extracted from a received signal and thereceived signal is demodulated by a digital signal processing circuit.In the digital coherent receiving method, since OSNR tolerance isimproved by coherent reception and waveform distortion is compensatedfor by a digital signal processing circuit, even an opticalcommunication system with 40 Gbit/s or more obtains a high reliability.A method for receiving optical QPSK signals by coherent detection isdescribed, for example, by D. Ly-Gagnon et al., “Coherent Detection ofOptical Quadrature Phase-Shift Keying Signals With Carrier PhaseEstimation”, IEEE, Journal of Lightwave Technology, vol. 24, No. 1, pp.12-21, January 2006.

FIG. 1 illustrates a configuration of a digital coherent opticalreceiver. In FIG. 1, a 90-degree optical hybrid circuit includes firstand second input ports and first and second output ports. An opticalsignal and local oscillator light are input to the first and secondinput ports, respectively. The local oscillator light is generated by alaser light source provided for a receiver. The optical signal and thelocal oscillator light are mixed and output from the first output port.The 90-degree optical hybrid circuit includes a 90-degree phase shiftelement. The optical signal and the local oscillator light whose phaseis shifted by 90 degrees are mixed and are output from the second outputport. One set of optical signals output from the first and second outputports are converted into electrical signals by respective photodetectors. Then the electrical signals are converted into digitalsignals by respective A/D converters and are given to the digital signalprocessing circuit.

One set of digital signals given to the digital signal processingcircuit indicate a real part component and a imaginary part component inthe case where an input optical signal is expressed by a complexelectric field. Then, the digital signal processing circuit demodulatesthe input optical signal using this set of digital signals.

When the 90-degree phase shift element has a phase error (quadratureerror or quadrature angle error) in the digital coherent opticalreceiver having the above configuration, crosstalk is caused between thereal part signal and the imaginary part signal. In this case, thedemodulation performance of the digital coherent optical receiverdeteriorates. In particular, in a modulation method whose spectral usageefficiency is high (that is, MPSK, MQAM and the like in which the numberof transmitted bits per symbol is large), since quality deterioration issensitive to the phase error of the 90-degree phase shift element, atechnique for compensating for the phase error is required.

As a method for compensating for the phase error of the 90-degreeoptical hybrid circuit, the following procedure is proposed. A method isprovided for correcting a quadrature angle error that exists in thecoherent receiver hardware of a dual-polarization optical transportsystem. The receiver hardware that causes the quadrature angle error isa 90 degree optical hybrid mixing device. The method involves generatingan estimate of the quadrature angle error and compensating for thequadrature angle error by multiplying the first and second detectedbaseband signals by coefficients that are a function of the estimate ofthe quadrature angle error. (for example, U.S. Pat. No. 6,917,031)

However, when the above method is realized by a hardware circuit, thecircuit scale increases. When the calculation speed of a processor istaken into account, it is difficult to realize the above method bysoftware in a receiver for receiving Gbit/s signals.

SUMMARY

According to an aspect of an invention, a digital coherent opticalreceiver provided with a 90-degree optical hybrid circuit for detectingan in-phase signal and a quadrature signal of an input optical signalincludes first through fourth circuits. The first circuit calculates asquare of a sum of the in-phase signal and the quadrature signal. Thesecond circuit subtracts a squared value of the in-phase signal and asquared value of the quadrature signal from the calculation result ofthe first circuit. The third circuit detects a phase error of the90-degree optical hybrid circuit based on the calculation result of thesecond circuit. The fourth circuit corrects at least one of the in-phasesignal and the quadrature signal according to the phase error detectedby the third circuit.

According to another aspect of an invention, a digital coherent opticalreceiver provided with a 90-degree optical hybrid circuit for detectingan in-phase signal and a quadrature signal of an input optical signalincludes an amplitude error compensation circuit and first throughfourth circuits. The amplitude error compensation circuit generates asecond in-phase signal by correcting the in-phase signal in such a waythat amplitude information about the in-phase signal coincides with atarget value and generate a second quadrature signal by correcting thequadrature signal in such a way that amplitude information about thequadrature signal coincides with the target value. The first circuitcalculates a square of a sum of the second in-phase signal and thesecond quadrature signal. The second circuit subtracts a squared valueof the second in-phase signal and a squared value of the secondquadrature signal from the calculation result of the first circuit. Thethird circuit detects a phase error of the 90-degree optical hybridcircuit based on the calculation result of the second circuit. Thefourth circuit corrects at least one of the second in-phase signal andthe second quadrature signal according to the phase error detected bythe third circuit.

According to another aspect of an invention, a digital coherent opticalreceiver provided with a 90-degree optical hybrid circuit for detectingan in-phase signal and a quadrature signal of an input optical signalincludes a phase error compensation circuit to generate a first signaland a second signal, which represent the in-phase signal and thequadrature signal whose phase error of the 90-degree optical hybridcircuit is compensated for, according to the in-phase signal and thequadrature signal. The phase error compensation circuit includes firstthrough fourth circuits. The first calculation circuit calculates asquare of a sum of the first signal and the second signal. The secondcircuit subtracts a squared value of the first signal and a squaredvalue of the second signal from the calculation result of the firstcircuit. The third circuit detects the phase error of the 90-degreeoptical hybrid circuit based on the calculation result of the secondcircuit. The fourth circuit generates the first signal and the secondsignal by correcting at least one of the in-phase signal and thequadrature signal according to the phase error detected by the thirdcircuit.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a configuration of a digital coherent opticalreceiver.

FIG. 2 illustrates a configuration of the digital coherent opticalreceiver in the embodiment.

FIG. 3 explains a phase error and an amplitude error.

FIG. 4 illustrates a configuration of the digital coherent opticalreceiver in the first embodiment.

FIG. 5 illustrates a configuration of the digital coherent opticalreceiver in the second embodiment.

FIG. 6 illustrates a feed-forward system for compensating for amplitudeerror.

FIG. 7 illustrates a variation (configuration without an amplitude errorcompensation circuit) of the digital coherent optical receiver in thesecond embodiment.

FIG. 8 illustrates a variation (configuration provided with an amplitudemonitor unit) of the digital coherent optical receiver in the secondembodiment.

FIG. 9 illustrates a configuration of the digital coherent opticalreceiver in the third embodiment.

FIG. 10 illustrates a variation (configuration without normalization) ofthe digital coherent optical receiver in the third embodiment.

FIG. 11 illustrates a variation (configuration without an amplitudeerror compensation circuit) of the digital coherent optical receiver inthe third embodiment.

DESCRIPTION OF EMBODIMENTS

FIG. 2 illustrates a configuration of the digital coherent opticalreceiver in the embodiment. The digital coherent optical receiver in theembodiment includes a 90-degree optical hybrid circuit 10, photodetectors 12 and 13, A/D converters 14 and 15, and a digital signalprocessing circuit 20.

The 90-degree optical hybrid circuit 10 includes first and second inputports and first and second output ports. An optical signal and localoscillator light are input to the first and second input ports,respectively. In this embodiment, the optical signal is transmitted froman optical transmitter, which is not illustrated, via an optical fibertransmission path and is received by the digital coherent opticalreceiver. The local oscillator light is generated by a laser lightsource, which is not illustrated, provided for the digital coherentoptical receiver. The optical signal and local oscillator light aremixed in, for example, an optical waveguide and the resultant lightwaveis guided to the first output port as an in-phase signal. The 90-degreeoptical hybrid circuit 10 includes a 90-degree phase shift element 11for shifting the phase of local oscillator light by 90 degrees. The90-degree phase shift element 11 may adjust the optical path length ofthe optical waveguide according to an applied voltage. The opticalsignal and the local oscillator light whose phase is shifted by 90degrees are mixed and output from the second output port as a quadraturesignal.

One set of optical signals (the in-phase signal and the quadraturesignal) output from the first and second output ports are converted intoelectrical signals by photo detectors (PD) 12 and 13, respectively. Forthe photo detectors 12 and 13, for example, photodiodes are used. TheA/D converters 14 and 15 convert one set of the electrical signalsobtained by the photo detectors 12 and 13, respectively, into digitalsignals and give the set of digital signals to the digital signalprocessing circuit 20. In this case, when the optical signal isexpressed by a complex electric field, the set of digital signalscorrespond to the real and imaginary part components of the inputoptical signal. Also in this case, the real and imaginary partcomponents correspond to the in-phase (I) and quadrature (Q) componentsof the optical signal. Therefore, the set of digital signals given tothe digital signal processing circuit 20 are sometimes called “real partcomponent” and “imaginary part component” below. Note that, in general,in-phase and quadrature signals are related to real and imaginary partsignals, respectively, however, in-phase and quadrature signals may alsobe related to real and imaginary part signals, respectively.

The digital signal processing circuit 20 includes a compensation circuit21, a waveform distortion compensation circuit 22, a phasesynchronization circuit 23, and a decision circuit 24. The compensationcircuit 21 compensates for phase error and amplitude error. The phaseerror corresponds to the error (quadrature error) of the 90-degree phaseshift element 11. The amplitude error indicates the imbalance in theaverage amplitude between the real part signal and the imaginary partsignal.

The waveform distortion compensation circuit 22 compensates for waveformdistortion caused in a transmission line. The waveform distortion iscaused, for example, by chromatic distribution, polarization modedistribution, and the like. Namely, the waveform distortion compensationcircuit 22 compensates for chromatic distribution, polarization modedistribution, and the like. The phase synchronization circuit 23establishes phase synchronization. The establishment of phasesynchronization includes a process for compensating for the frequencyand phase error of carrier wave light for propagating the optical signaland the local oscillator light. The decision circuit 24 recovers datafrom the real part signal and the imaginary part signal for each symbol.Specifically, the input optical signal is demodulated and thetransmission data is recovered. In the QPSK system, for example, twobits of transmission data are recovered based on the real and imaginarypart signals for each symbol.

FIG. 2 illustrates a digital coherent receiver without a polarizationdiversity configuration. However, the configuration illustrated in FIG.2 may be applied to a polarization diversity receiver. The polarizationdiversity receiver has a polarization beam splitter and a pair ofdigital coherent receivers. The polarization beam splitter generates apair of orthogonally polarized signals of the input signal. The pair ofdigital coherent receivers recover data from the pair of orthogonallypolarized signals, respectively. In this case, each of the digitalcoherent receivers of the polarization diversity receiver may berealized by the receiver illustrated in FIG. 2. Note that a digitalcoherent receiver without a polarization diversity configuration will betaken as an example and explained below.

FIG. 3 explains a phase error and an amplitude error. In this case, itis assumed that the real and imaginary components of a certain symbolare expressed by (I₀, Q₀). In addition, it is assumed that the phase ofthe 90-degree phase shift element 11 is exactly set to 90 degrees andthat there is no amplitude imbalance. The real and imaginary componentsto be input to the digital signal processing circuit 20 are I₀ and Q₀,respectively.

However, it is not easy to precisely adjust the phase of the 90-degreephase shift element 11 to 90 degrees. The phase of the 90-degree phaseshift element 11 changes depending on temperature, aging deterioration,or the like. Therefore, in FIG. 3, the phase of the 90-degree phaseshift element 11 has an error θ with respect to “quadrature angle”. Thiserror is sometimes called “phase error” or “quadrature error”.

In this case, the real and imaginary part signals I₁ and Q₁,respectively, input to the digital processing circuit 20 are expressedby the following expression. α represents the imbalance in amplitudebetween the real and imaginary part signals.

I₁=I₀

Q ₁=α(I ₀ sin θ+Q ₀ cos θ)

Namely, the input signal of the digital signal processing circuit 20 isexpressed according to expression (1).

$\begin{matrix}{\begin{bmatrix}I_{1} \\Q_{1}\end{bmatrix} = {\begin{bmatrix}1 & 0 \\{\alpha \; {\sin (\theta)}} & {\alpha \; {\cos (\theta)}}\end{bmatrix}\begin{bmatrix}I_{0} \\Q_{0}\end{bmatrix}}} & (1)\end{matrix}$

When the 90-degree optical hybrid circuit 10 has a phase error θ,crosstalk occurs between the real and imaginary part signals. In thiscase, a demodulation performance deteriorates. Therefore, the digitalcoherent optical receiver in the embodiment includes the compensationcircuit 21 to compensate for the phase error θ (and amplitude imbalanceα) caused in the 90-degree optical hybrid circuit 10.

The digital signal processing circuit 20 may be realized by a hardwarecircuit or by using a processor for executing a software program.However, in order to process several tens of Gbit/s signals, it ispreferable that the digital signal processing circuit 20 be realized bya hardware circuit that can calculate at high speed. In this case, thehardware circuit may be realized as an ASIC.

First Embodiment

FIG. 4 illustrates a configuration of the digital coherent opticalreceiver in the first embodiment. FIG. 4 describes the 90-degree opticalhybrid circuit 10 and compensation circuit 21 that are illustrated inFIG. 2. In FIG. 4, the photo detectors (PD) 12 and 13, and A/Dconverters 14 and 15 that are illustrated in FIG. 2 are omitted.

The digital coherent optical receiver in the first embodiment includesfirst through fourth circuits 21 a-21 d. As explained with reference toFIGS. 2 and 3, the 90-degree optical hybrid circuit 10 generates thereal part signal I₁ and the imaginary part signal Q₁ for respectivelyrepresenting the real and imaginary components of an input opticalsignal. In the following description it is assumed that the in-phase andquadrature signals of the input optical signal are related to the realand imaginary components, respectively, in a complex electric field. Thefirst through fourth circuits 21 a-21 d may be realized by the digitalsignal processing circuit.

The first circuit 21 a calculates the square of the sum of the real andimaginary part signals. Specifically, (I₁+Q₁)² is obtained by the firstcircuit 21 a. The second circuit 21 b subtracts the squared value of thereal part signal and the squared value of the imaginary part signal fromthe calculation result of the first circuit 21 a. Specifically,(I₁+Q₁)²−(I₁ ²+Q₁ ²) is calculated by the second circuit 21 b. In thiscase, the second circuit may calculate the sum (I₁ ²+Q₁ ²) of thesquared value of the real part signal and the squared value of theimaginary part signal, and then subtract the sum from the calculationresult of the first circuit 21 a. Alternatively, the second circuit 21 bmay individually subtract I₁ ² and Q₁ ² from the calculation result ofthe first circuit 21 a. 2I₁Q₁ is obtained by the second circuit 21 b bycalculating according to one of the procedures. The third circuit 21 cdetects the phase error of the 90-degree optical hybrid circuit 10,using the calculation result of the second circuit 21 b. Then, thefourth circuit 21 d corrects at least one of the real part signals I₁and the imaginary part signal Q₁ according to the phase error detectedby the third circuit 21 c.

In this case, crosstalk between the real and imaginary part signals inthe case where the 90-degree optical hybrid circuit 10 has a phase errorθ depends on the calculation result of the second circuit 21 b.Therefore, the phase error of the 90-degree optical hybrid circuit 10 iscompensated for by correcting the real part signal I₁ and the imaginarypart signal Q₁ using the calculation result of the second circuit 21 b.

The first circuit 21 a may individually receive I₁ and Q₁ to calculate(I₁+Q₁)² or may receive the sum I₁+Q₁ to calculate (I₁+Q₁)². The fourthcircuit 21 d may correct the real and imaginary part signals by eitherfeed-forward or feedback system. Furthermore, the digital coherentoptical receiver in the first embodiment may further include a circuitfor compensating for an amplitude error.

Second Embodiment

FIG. 5 illustrates a configuration of the digital coherent opticalreceiver in the second embodiment. The digital coherent optical receiverin the second embodiment includes an I-Q amplitude error compensationcircuit 30 and an I-Q phase error compensation circuit 40. In the secondembodiment, the I-Q phase error compensation circuit 40 compensates foran I-Q phase error by a feed-forward method. It is assumed that the realpart signal I₁ and the imaginary part signal Q₁ illustrated in the aboveexpression (1) are input to the digital coherent optical receiver foreach symbol. Each of I₁ and Q₁ are a predetermined number of bits ofdigital data.

The I-Q amplitude error compensation circuit 30 includes a squaringcircuit 31 a, an averaging circuit 32 a, a differential circuit 33 a, amultiplier 34 a, an accumulation adder 35 a, and a multiplier 36 a inorder to correct the real part signal I₁. In the following description,a signal output from the multiplier 36 a is called I₂.

The squaring circuit 31 a squares the signal I₂. The averaging circuit32 a averages the signal I₂ ² output from the squaring circuit 31 a. Atthis moment, the averaging circuit 32 a calculates the average of theoutput signals of the squaring circuit 31 a for a plurality of symbols(for example, several symbols through several tens of symbols). Thedifferential circuit 33 a calculates a difference between the outputsignal of the averaging circuit 32 a and a target value. The calculationresult of the differential circuit 33 a is output as an error signal.The target value is, for example, 1 or 2^(N) (N is an integer), thoughthe embodiment is not limited to this value.

The multiplier 34 a multiplies the error signal obtained by thedifferential circuit 33 a by a specified constant. This constant is astep size for determining the response speed of a control loop and issufficiently small. The accumulation adder 35 a calculates theaccumulation value of the calculation result of the multiplier 34 a.Specifically, the accumulation adder 35 a operates as an integrator.Then, the multiplier 36 a generates the signal I₂ by multiplying thereal part signal I₁ by the calculation result of the accumulation adder35 a.

In this case, the mean square of the real part signal I₁ (that is, theaverage of I₁ ²) is basically constant. For example, in a QPSK system,since four signal points (1,1), (1,−1), (−1,−1) and (−1,1) are used, themean square of the input real part signal I₁ is 1. Here, the outputsignal of the accumulation adder 35 a is constant, as described later.Thus, the signal I₂, which is obtained by multiplying the input realpart signal I₁ by the output signal of the accumulation adder 35 a, isalso a constant. Accordingly, the output signal of the averaging circuit32 a is almost constant.

The above feedback system operates in such away that the output signalof the differential circuit 33 a may become zero. Specifically, theoutput signal of the averaging circuit 32 a coincides with the targetvalue. As a result, the output signal of the accumulation adder 35 aconverges on a certain value. This value is referred to a “normalizationcoefficient a”. Thus, the I-Q amplitude error compensation circuit 30generates the signal I₂ by multiplying the real part signal I₁ by thenormalization coefficient a.

The I-Q amplitude error compensation circuit 30 further includes asquaring circuit 31 b, an averaging circuit 32 b, a differential circuit33 b, a multiplier 34 b, an accumulation adder 35 b, and a multiplier 36b in order to correct the imaginary part signal Q₁. The configurationsand operations of the squaring circuit 31 b, the averaging circuit 32 b,the differential circuit 33 b, the multiplier 34 b, the accumulationadder 35 b, and the multiplier 36 b are basically the same as those ofthe squaring circuit 31 a, the averaging circuit 32 a, the differentialcircuit 33 a, the multiplier 34 a, the accumulation adder 35 a, and themultiplier 36 a, respectively.

Specifically, this feedback system (31 b-36 b) operates in such a waythat the output signal Q₂ ² of the averaging circuit 32 b coincides withthe target value. In this case, this target value is the same as thetarget value used in order to correct the real part signal. However, inthis embodiment, real and imaginary part signals may have the amplitudeimbalance α. Therefore, the output signal of the accumulation adder 35 bconverges on a/α. Accordingly, the I-Q amplitude error compensationcircuit 30 generates the signal Q₂ by multiplying the imaginary partsignal Q₁ by the coefficient a/α.

The signals I₂ and Q₂ obtained by the I-Q amplitude error compensationcircuit 30 are given to the I-Q phase error compensation circuit 40. Atthis time, the I-Q amplitude error of the signals I₂ and Q₂ has beencompensated for and both of the amplitude of the signals I₂ and Q₂ hasbeen normalized. The signal process by the I-Q amplitude errorcompensation circuit 30 is expressed by expression (2).

$\begin{matrix}\begin{matrix}{\begin{bmatrix}I_{2} \\Q_{2}\end{bmatrix} = {{{a\begin{bmatrix}1 & 0 \\0 & {1/\alpha}\end{bmatrix}}\begin{bmatrix}1 & 0 \\{\alpha \; {\sin (\theta)}} & {\alpha \; {\cos (\theta)}}\end{bmatrix}}\begin{bmatrix}I_{0} \\Q_{0}\end{bmatrix}}} \\{= {{a\begin{bmatrix}1 & 0 \\{\sin (\theta)} & {\cos (\theta)}\end{bmatrix}}\begin{bmatrix}I_{0} \\Q_{0}\end{bmatrix}}}\end{matrix} & (2)\end{matrix}$

Not only the signals I₂ and Q₂ but also the output signals of thesquaring circuits 31 a and 31 b are given to the I-Q phase errorcompensation circuit 40. In this case, the output signals of thesquaring circuits 31 a and 31 b are I₂ ² and Q₂ ², respectively.

The I-Q phase error compensation circuit 40 includes an adder 41, asquaring circuit 42, an adder 43, a subtractor 44, a divider 45, anaveraging circuit 46, a divider 47, a squaring circuit 48, a subtractor49, a square root calculator 50, a multiplier 51, a multiplier 52, and asubtractor 53.

The adder 41 calculates the sum of signals I₂ and Q₂. Specifically,I₂+Q₂ is calculated. The squaring circuit 42 squares the output signalof the adder 41. Specifically, (I₂+Q₂)² is calculated. The adder 43calculates the sum of signals I₂ ² and Q₂ ². Specifically, I₂ ²+Q₂ ² iscalculated. The subtractor 44 subtracts the output signal of the adder43 from the output signal of the squaring circuit 42. The divider 45divides the output signal of the subtractor 44 by “2”. Then, theaveraging circuit 46 averages the output signals of the divider 45. Inthis case, the averaging circuit 46 calculates the average value of theoutput signals of the divider 45 for a plurality of symbols (forexample, several through several tens of symbols).

The output signal of the averaging circuit 46 is expressed by thefollowing expression (3). In the above expression, “N” is the number ofsymbols used by the averaging circuit 46.

Σ{{(I ₂ +Q ₂)²−(I ₂ ² +Q ₂ ²)}/2}/N  (3)

When expression (3) is developed, expression (4) can be obtained.

$\begin{matrix}{{\sum{\left\{ {\left\{ {\left( {I_{2} + Q_{2}} \right)^{2} - \left( {I_{2}^{2} + Q_{2}^{2}} \right)} \right\}/2} \right\}/N}} = {{\sum{\left\{ {\left\{ {\left( {I_{2}^{2} + {2I_{2}Q_{2}} + Q_{2}^{2}} \right) - \left( {I_{2}^{2} + Q_{2}^{2}} \right)} \right\}/2} \right\}/N}} = {{\sum{\left\{ {2I_{2}{Q_{2}/2}} \right\}/N}} = {\sum{\left\{ {I_{2}Q_{2}} \right\}/N}}}}} & (4)\end{matrix}$

In the above expression, I₂ and Q₂ may be expressed by the aboveexpression (2). Therefore, the output signal of the averaging circuit 46is expressed by the following expression (5).

$\begin{matrix}\begin{matrix}{{\sum\left\{ {I_{2}Q_{2}} \right\}} = {\sum\left\{ {\left( {a\; I_{0}} \right)\left( {{a\; I_{0}\sin \; \theta} + {a\; Q_{0}\cos \; \theta}} \right)} \right\}}} \\{= {\sum\left\{ {a^{2}{I_{0}\left( {{I_{0}\sin \; \theta} + {Q_{0}\cos \; \theta}} \right)}} \right\}}} \\{= {\sum\left\{ {a^{2}\left( {{I_{0}^{2}\sin \; \theta} + {I_{0}Q_{0}\cos \; \theta}} \right)} \right\}}}\end{matrix} & (5)\end{matrix}$

In this case, it is assumed that data propagated by the optical signalis a random bit string. If so, there is no correlation between I₀ andQ₀. Therefore, ΣI₀Q₀ becomes zero. Accordingly, in this case, the outputsignal of the averaging circuit 46 may be expressed by the followingexpression (6).

sin θΣ{a ² I ₀ ² }/N  (6)

The divider 47 divides the output signal of the averaging circuit 46 bya target value. This target value is the same as that used in the I-Qamplitude error compensation circuit 30. In this case, in the feedbacksystem of the I-Q amplitude error compensation circuit 30, the averagingcircuit 32 a calculates the average of the square of the signal I₂ andit is controlled in such a way that the output signal of the averagingcircuit 32 a may coincide with the target value. Therefore, this targetvalue may be expressed by Σ{a²I₀ ²}/N.

If so, the output of the divider 47 is expressed by the followingexpression (7).

$\begin{matrix}\begin{matrix}{{{\left\{ {\sin \; \theta {\sum{\left\{ {a^{2}I_{0}^{2}} \right\}/N}}} \right\}/{target}}\mspace{14mu} {value}} = {\left\{ {\sin \; \theta {\sum{\left\{ {a^{2}I_{0}^{2}} \right\}/N}}} \right\}/}} \\{= \left\{ {\sum{\left\{ {a^{2}I_{0}^{2}} \right\}/N}} \right.} \\{= {\sin \; \theta}}\end{matrix} & (7)\end{matrix}$

In the above expression, θ is the phase error of the 90-degree opticalhybrid circuit 10. Specifically, in the second embodiment, the phaseerror of the 90-degree optical hybrid circuit 10 is detected by theoutput signal of the divider 47.

The squaring circuit 48 squares the output signal of the divider 47.Specifically, sin₂ θ is calculated by the squaring circuit 48. Thesubtractor 49 calculates 1−sin₂ θ by subtracting the output signal ofthe squaring circuit 48 from “1”. The square root calculator 50calculates the square root of the output signal of the subtractor 49. Asa result, cos θ is obtained. Furthermore, the multiplier 51 multipliesthe signal I₂ by the output signal of the square root calculator 50.Specifically, I₂ cos θ is calculated. Then, the calculation result ofthe multiplier 51 is output as a signal I₃.

In this case, the signal I₂ is aI₀ as expressed by expression (2).Therefore, the signal I₃ is expressed by the following expression (8).

Signal I₃=I₂ cos θ=aI₀ cos θ  (8)

The multiplier 52 multiplies the signal I₂ by the output signal of thedivider 47. Specifically, I₂ sin θ is calculated. The subtractor 53subtracts the output signal of the multiplier 52 from the signal Q₂.Then, the calculation result of the subtractor 53 is output as a signalQ₃. In this case, the signal Q₂ is a (I₀ sin θ+Q₀ cos θ), as represented by expression (2). Therefore, the signal Q₃ is expressed byexpression (9).

$\begin{matrix}\begin{matrix}{{{Signal}\mspace{14mu} Q_{3}} = {Q_{2} - {I_{2}\sin \; \theta}}} \\{= {{a\left( {{I_{0}\sin \; \theta} + {Q_{0}\cos \; \theta}} \right)} - {a\; I_{0}\sin \; \theta}}} \\{= {a\; Q_{0}\cos \; \theta}}\end{matrix} & (9)\end{matrix}$

When the above expressions (8) and (9) are expressed in a matrix form,expression (10) is obtained.

$\begin{matrix}{\begin{bmatrix}I_{3} \\Q_{3}\end{bmatrix} = {{\begin{bmatrix}{\cos (\theta)} & 0 \\{- {\sin (\theta)}} & 1\end{bmatrix}{{a\begin{bmatrix}1 & 0 \\{\sin (\theta)} & {\cos (\theta)}\end{bmatrix}}\begin{bmatrix}I_{0} \\Q_{0}\end{bmatrix}}} = {a\; {{\cos (\theta)}\begin{bmatrix}I_{0} \\Q_{0}\end{bmatrix}}}}} & (10)\end{matrix}$

Thus, the output signals I₃ and Q₃ of the I-Q phase error compensationcircuit 40 is expressed by the following expressions.

I₃=aI₀ cos θ

Q₃=aQ₀ cos θ

In this case, the signal I₃ does not include the Q₀ component.Similarly, the signal Q₃ does not include the I₀ component. Therefore,neither the signal I₃ nor Q₃ includes a crosstalk component. “a cos θ”is common to the signals I₃ and Q₃. Therefore, the original real andimaginary components I₀ and Q₀ of the optical signal are obtained basedon the signals I₃ and Q₃. In this case, “a” and “cos θ” do not change ina short time. Specifically, I₃:Q₃=I₀:Q₀. Therefore, for example, whenthe optical signal carries data using phase modulation, such as QPSK orthe like, the modulation phase of each symbol may be preciselycalculated according to a ratio between the signals I₃ and Q₃. Inaddition, when the optical signal carries data using QAM or the like,the modulation phase and amplitude of each symbol may be preciselycalculated using I₃, Q₃ and

I₃ ²+Q₃ ².

Thus, according to the digital coherent optical receiver in the secondembodiment, the phase error of the 90-degree optical hybrid circuit iscompensated for and the original real and imaginary components I₀ and Q₀of an input optical signal are obtained. Therefore, the demodulationperformance is improved.

In the embodiment illustrated in FIG. 5, the I-Q phase errorcompensation circuit 40 includes two dividers 45 and 47. In this case,when the divider is realized by a hardware circuit, generally thecircuit scale increases. However, the function of the divider 45 is todivide the output signal of the subtractor 44 by “2”. Therefore, thedivider 45 is realized by a bit shift circuit. The circuit size of thebit shift circuit is generally small.

The divider 47 divides the output signal of the averaging circuit 46 bya target value. This target value is a constant used in the controlsystem of the I-Q amplitude error compensation circuit 30 and a desiredvalue may be selected. In this embodiment, the target value is, forexample, “1”. In this case, the divider 47 divides the output signal ofthe averaging circuit 46 by “1”. Therefore, in this case, the I-Q phaseerror compensation circuit 40 may be configured without the divider 47.In this case, the phase error of the 90-degree optical hybrid circuit 10is detected by the output signal of the averaging circuit 46. The abovetarget value may also be, for example, “2^(N)”. In this case, thedivider 47 may be realized by a bit shift circuit. Thus, if anappropriate value is selected as the target value, the divider 47 may bedeleted or the circuit scale of the divider 47 may be reduced.

The I-Q phase error compensation circuit 40 uses I₂ ² and Q₂ ² in orderto compensate for phase error. However, I₂ ² and Q₂ ² are calculated bythe I-Q amplitude compensation circuit 30. Then, the I-Q phase errorcompensation circuit 40 compensates for phase error using the I₂ ² andQ₂ ² that are calculated by the I-Q amplitude compensation circuit 30.In this configuration, since the I-Q phase error compensation circuit 40dose not need to include respective circuits for squaring the signals I₂and Q₂, the circuit scale of the I-Q phase error compensation circuit 40may be reduced.

Furthermore, the I-Q phase error compensation circuit 40 calculates I₂Q₂using the adder 41, the squaring circuit 42, the adder 43, and thesubtractor 44 without using multipliers. In this case, the circuitscales of an adder, a squaring circuit, and a subtractor are smallerthan a multiplier. Therefore, the circuit scale of the I-Q phase errorcompensation circuit 40 may be reduced. The I-Q phase error compensationcircuit 40 may individually subtract I₁ ² and Q₁ ² from (I₂+Q₂)² withoutincluding the adder 43.

In the embodiment illustrated in FIG. 5, after an amplitude imbalance iscompensated for by the I-Q amplitude compensation circuit 30, the I-Qphase error compensation circuit 40 compensates for a phase error.However, the second embodiment is not limited to this configuration. Inother words, in the second embodiment, after the I-Q phase errorcompensation circuit 40 compensates for a phase error, an amplitudeerror may be compensated for.

Variation 1 of Second Embodiment

In the embodiment illustrated in FIG. 5, a feedback system is configuredin such a way that the respective averages of I₂ ² and Q₂ ² may coincidewith their target values in the I-Q amplitude compensation circuit 30.However, the feedback system may operate in such a way that therespective averages of the absolute values of the signals I₂ and Q₂ maycoincide with the corresponding target value. In this case, the I-Qamplitude compensation circuit 30 includes a circuit for calculating theabsolute value of an input signal instead of the squaring circuits 31 aand 31 b.

The absolute values of real/imaginary part signals correspond to the“amplitude” of signals representing the real/imaginary components of anoptical signal. The squared value of real/imaginary part signals are thesquare of their amplitude. Therefore, both the absolute values and thesquared values of real/imaginary part signals are “amplitudeinformation” about signals representing real/imaginary components of theoptical signal.

Variation 2 of Second Embodiment

In the embodiment illustrated in FIG. 5, the I-Q amplitude compensationcircuit 30 compensates for amplitude errors by feedback control.However, the I-Q amplitude compensation circuit 30 may compensate foramplitude errors by feed-forward control.

FIG. 6 is a feed-forward system for compensating for amplitude error.The feed-forward system is provided in order to correct respective realand imaginary part signals. These feed-forward systems in a circuit forcorrecting the real part signal and in a circuit for the imaginary partsignal are the same. This forward system includes a squaring circuit 61,an averaging circuit 62, a subtractor 63 and a multiplier 64.

In the circuit for correcting the real part signal, the squaring circuit61 squares the signal I₁. The averaging circuit 62 averages the outputsignal of the squaring circuit 61. The subtractor 63 calculates adifference between the target value and the output signal of theaveraging circuit 62. Then, multiplier 64 generates the signal I₂ bymultiplying the signal I₁ by the above difference. In the circuit forcorrecting the imaginary part signal, the signal Q₂ is generated fromthe signal Q₁ in the similar way. In the feed-forward system illustratedin FIG. 6, the absolute values of signals I₁ and Q₁ may be used insteadof the square of signals I₁ and Q₁.

Variation 3 of Second Embodiment

The digital coherent optical receiver illustrated in FIG. 5 includes theI-Q amplitude compensation circuit 30 and the I-Q phase errorcompensation circuit 40. However, the digital coherent optical receiverillustrated in FIG. 7 does not include the I-Q amplitude compensationcircuit 30. In other words, the digital coherent optical receiverillustrated in FIG. 7 may be used, for example, when received opticalsignal has no or small I-Q amplitude error (for example, when α≅1 in theexpression 1).

In this configuration, the digital coherent optical receiver includesthe I-Q phase error compensation circuit 40 illustrated in FIG. 5. Theconfiguration and operation of the I-Q phase error compensation circuit40 are basically as explained with reference to FIG. 5.

However, in this configuration, I₁, Q₁, I₁ ² and Q₁ ² are input for eachsymbol. The adder 41, the squaring circuit 42, the adder 43, thesubtractor 44, the divider 45, and the averaging circuit 46 perform thesame calculations as in the configuration illustrated in FIG. 5 to theseinput signals. In this case it is assumed that an I-Q amplitude errordoes not exist or is small and that “α=1” in expression (1). If so, theoutput signal of the averaging circuit 46 is expressed by

ΣI₀ ² sin θ/N.

The divider 47 calculates τI₁ ² and further divides the output signal ofthe averaging circuit 46 by ΣI₁ ²/N. In this case, ΣI₁ ²/N is theaverage of the square of the signal I₁. A circuit for calculating theaverage of the square of the signal I₁ may be realized, for example, bythe same circuit as the squaring circuit 31 a and averaging circuit 32 aillustrated in FIG. 5. Alternatively, ΣI₁ ²/N may be calculated byaveraging I₁ ² for each symbol.

The output signal of the divider 47 is expressed by the followingexpression.

(ΣI ₀ ² sin θ/N)/(ΣI ₁ ² /N)=ΣI ₀ ² sin θ/ΣI ₁ ²=sin θ

A configuration for correcting the real and imaginary part signals usingthe output signal of the divider 47 (that is, sin θ) is basically thesame as the configuration illustrated in FIG. 5. A cos θ calculationcircuit 54 calculates cos θ based on sin θ. In this case, the cos θcalculation circuit 54 may be realized by the squaring circuit 48, thesubtractor 49, and the square root calculator 50 illustrated in FIG. 5or by another circuit configuration.

Variation 4 of Second Embodiment

A digital coherent optical receiver generally has a function to monitorthe amplitude or power of an input optical signal and to detect whetherthere is an optical signal. In the configuration illustrated in FIG. 8,the phase error of real/imaginary part signals is compensated for byusing the information detected by this monitor function.

The digital coherent optical receiver illustrated in FIG. 8 includes anamplitude monitor unit 71. The amplitude monitor unit 71 receives thesignals I₁ and Q₁ and calculates amplitude information I₁ ²+Q₁ ². Theamplitude information is transmitted to a detector for detecting whetherthere is an optical signal, which is not illustrated, and also given tothe I-Q phase error compensation circuit 40.

The configuration and operation of the I-Q phase error compensationcircuit illustrated in FIG. 8 is basically the same as the configurationillustrated in FIG. 7. However, in the configuration illustrated in FIG.8, since I₁ ²+Q₁ ² is given from the amplitude monitor unit 71, theadder 43 is not provided. Then, the subtractor 44 subtracts I₁ ²+Q₁ ²given from the amplitude monitor unit 71 from the output signal of thesquaring circuit 42.

According to this configuration, the I-Q phase error compensationcircuit 40 does not need to include respective circuits for squaringsignals I₂ and Q₂. Therefore, the circuit scale of the I-Q phase errorcompensation circuit 40 may be reduced.

Third Embodiment

FIG. 9 illustrates a configuration of the digital coherent opticalreceiver in the third embodiment. The digital coherent optical receiverin the third embodiment includes I-Q amplitude error compensationcircuits 30A and 30B and I-Q phase error compensation circuit 80. In thethird embodiment, the I-Q phase error compensation circuit 80compensates for I-Q phase error by a feedback method. In the thirdembodiment, the following real and imaginary part signals I₁ and Q₁ areinput to the digital coherent optical receiver for each symbol.

I₁=I₀

Q ₁=α(I ₀ sin θ+Q ₀ cos θ)

Signals I₂ and Q₂ are input signals to the I-Q amplitude errorcompensation circuits 30A and 30B, respectively. However, I₁=I₂. Thesignal Q₂ is the output signal of the subtractor 90. Signals I₃ and Q₃are the output signals of the digital coherent optical receiver and realand imaginary part signals whose phase error and amplitude error arecompensated for.

In this embodiment, the I-Q phase error compensation circuit 80 includesan adder 81, a squaring circuit 82, an adder 83, a subtractor 84, adivider 85, an averaging circuit 86, a multiplier 87, an accumulationadder 88, a multiplier 89, and a subtractor 90.

The configurations and operations of the adder 81, the squaring circuit82, the adder 83, the subtractor 84, the divider 85 and the averagingcircuit 86 are similar to the adder 41, the squaring circuit 42, theadder 43, the subtractor 44, the divider 45, and the averaging circuit46 in the second embodiment. However, I₃, Q₃, I₃ ² and Q₃ ² are given tothe I-Q phase error compensation circuit 80. Therefore, the outputsignal of the averaging circuit 86 is Σ(I₃Q₃)/N. As described above, I₃and Q₃ are the output signals of this digital coherent optical receiver.In this embodiment, I₃ ² and Q₃ ² are calculated by the I-Q amplitudeerror compensation circuits 30A and 30B, respectively.

The multiplier 87 multiplies the output signal of the averaging circuit86 (that is, Σ(I₃Q₃)/N) by a specified constant. This constant is a stepsize for determining the response speed of a control loop and is asufficiently small value. The accumulation adder 88 calculates theaccumulation value of the calculation results of the multiplier 87. Inother words, the accumulation adder 88 operates as an integrator.

The multiplier 89 multiplies the real part signal I₁ by the calculationresult of the accumulation adder 88. Then, the subtractor 90 generatesthe signal Q₂ by subtracting the output signal of the multiplier 89 fromthe imaginary part signal Q₁.

The above feedback system operates in such away that the output signalof the averaging circuit 86 (that is, Σ(I₃Q₃)/N) may converge on zero.If so, the output signal of the accumulation adder 88 converges on α sinθ. In this case, the output signal of the multiplier 89 is αI₁ sin θ andthe output signal of the subtractor 90 (that is, signal Q₂) is Q₁−αI₁sin θ. Therefore, the signal Q₂ is expressed by the following expression(11).

$\begin{matrix}\begin{matrix}{Q_{2} = {Q_{1} - {\alpha \; I_{1}\sin \; \theta}}} \\{= {{\alpha \left( {{I_{0}\sin \; \theta} + {Q_{0}\cos \; \theta}} \right)} - {\alpha \; I_{1}\sin \; \theta}}} \\{= {\alpha \; Q_{0}\cos \; \theta}}\end{matrix} & (11)\end{matrix}$

When expressing the signals I₂ and Q₂ in a matrix form, expression (12)is obtained.

$\begin{matrix}\begin{matrix}{\begin{bmatrix}I_{2} \\Q_{2}\end{bmatrix} = {{\begin{bmatrix}1 & 0 \\{{- \alpha}\; {\sin (\theta)}} & 1\end{bmatrix}\begin{bmatrix}1 & 0 \\{\alpha \; {\sin (\theta)}} & {\alpha \; {\cos (\theta)}}\end{bmatrix}}\begin{bmatrix}I_{0} \\Q_{0}\end{bmatrix}}} \\{= {\begin{bmatrix}1 & 0 \\0 & {\alpha \; {\cos (\theta)}}\end{bmatrix}\begin{bmatrix}I_{0} \\Q_{0}\end{bmatrix}}}\end{matrix} & (12)\end{matrix}$

Thus, the signals I₂ and Q₂ obtained by the I-Q phase error compensationcircuit 80 is expressed by the following expression.

I₂=I₀

Q₂=αQ₀ cos θ

In this case, the signal I₂ does not include Q₀ component. Similarly,the signal Q₂ does not include I₀ component. Therefore, neither of thesignals I₂ and Q₂ includes any crosstalk component. However, in thisstage, the amplitude error α remains.

The configurations of the I-Q amplitude error compensation circuits 30Aand 30B are similar to that of the amplitude error compensation circuit30 illustrated in FIG. 5. Specifically, the I-Q amplitude errorcompensation circuit 30A operates in such a way that ΣI₃ ²/N maycoincide with the “target value”. The I-Q amplitude error compensationcircuit 30B operates in such a way that ΣQ₃ ²/N may coincide with thesame “target value”. Therefore, the calculation representing theoperation of the I-Q amplitude error compensation circuits 30A and 30Bmay be expressed by the expression (13).

$\begin{matrix}{a\begin{bmatrix}1 & 0 \\0 & {1/\left( {\alpha \; {\cos (\theta)}} \right)}\end{bmatrix}} & (13)\end{matrix}$

In this case, signals I₂ and Q₂ are given to the I-Q amplitude errorcompensation circuits 30A and 30B, respectively. Therefore, the signalsI₃ and Q₃ are obtained by applying the above expression (13) to thesignals I₂ and Q₂ expressed by the above expression (12). Specifically,the signals I₃ and Q₃ are calculated by the following expression (14).

$\begin{matrix}{\begin{bmatrix}I_{3} \\Q_{3}\end{bmatrix} = {{{{a\begin{bmatrix}1 & 0 \\0 & {1/\left( {\alpha \; {\cos (\theta)}} \right)}\end{bmatrix}}\begin{bmatrix}1 & 0 \\0 & {\alpha \; {\cos (\theta)}}\end{bmatrix}}\begin{bmatrix}I \\Q\end{bmatrix}} = {a\begin{bmatrix}I_{0} \\Q_{0}\end{bmatrix}}}} & (14)\end{matrix}$

Therefore, the signals I₃ and Q₃ obtained by this digital coherentoptical receiver are expressed by the following expression.

I₃=aI₀

Q₃=aQ₀

Thus, neither of the signals I₃ and Q₃ includes crosstalk component. “a”is common to the signals I₃ and Q₃. Therefore, the original real andimaginary part components I₀ and Q₀ of an optical signal are obtainedbased on the signals I₃ and Q₃. In other words, as in the first orsecond embodiment, in the digital coherent optical receiver in the thirdembodiment, the phase error of the 90-degree optical hybrid circuit iscompensated for and the original real and imaginary part components I₀and Q₀ of the optical signal are obtained. Therefore, the modulationperformance is improved.

Since phase error are compensated for by feedback control in the thirdembodiment, the operation of the I-Q phase error compensation circuit 80does not depend on the target value used in the I-Q amplitude errorcompensation circuits 30A and 30B. Therefore, in the third embodiment,no divider is needed between the averaging circuit 86 and the multiplier87. In addition, in the third embodiment, as in the first or secondembodiment, the I-Q amplitude error compensation circuits 30A and 30Bmay compensate for amplitude error using the absolute value of thesignals I₃ and Q₃. Furthermore, as in the first or second embodiment, inthe third embodiment, the I-Q amplitude error compensation circuits 30Aand 30B may compensate for amplitude error by feed-forward control. Inaddition, the circuit scale is reduced by the configuration of the thirdembodiment.

Alternatively, I₁ ² and Q₁ ² may be individually subtracted from(I₂+Q₂)² without providing the adder 83 in the I-Q phase errorcompensation circuit 80 in the third embodiment. Furthermore, in theembodiment illustrated in FIG. 9, the I-Q phase error compensationcircuit 80 compensates for a phase error before the I-Q amplitude errorcompensation circuits 30A and 30B compensate for amplitude imbalance.However, the amplitude error may be compensated for before the I-Q phaseerror compensation circuit 80 compensates for the phase error.

Variation 1 of Third Embodiment

FIG. 10 illustrates a variation (configuration without normalization) ofthe digital coherent optical receiver in the third embodiment. In thisconfiguration, the I-Q amplitude error compensation circuit does notperform normalization. In this case, the I-Q amplitude errorcompensation circuit includes a squaring circuit 91, an averagingcircuit 92, a squaring circuit 93, an averaging circuit 94, a subtractor95, a multiplier 96, an accumulation adder 97 and a multiplier 98. Inthis configuration, the signal I₁ is output without being changed.

The squaring circuit 91 squares a signal I₃. The averaging circuit 92calculates the average of the output signal of the squaring circuit 91.Similarly, the squaring circuit 93 squares a signal Q₃ and the averagingcircuit 94 calculates the average of the output signal of the squaringcircuit 93. Then, the subtractor 95 calculates a difference between theoutput signal of the averaging circuit 92 and the output signal of theaveraging circuit 94.

The multiplier 96 multiplies the difference obtained by the subtractor95 by the step size. The accumulation adder 97 calculates anaccumulation value of the output signal from the multiplier 96. Themultiplier 98 multiplies the signal Q₂ by the output signal of theaccumulation adder 97.

The feedback system operates in such a way that the difference obtainedby the subtractor 95 may converge on zero. Thus, the signal Q₂ iscorrected and the signal Q₃ is generated.

The circuit for compensating for phase error is a feedback system andhas the similar configuration as illustrated in FIG. 9. However, in theconfiguration illustrated in FIG. 10, a phase error is compensated forusing I₃ ² and Q₃ ² calculated by the squaring circuits 91 and 93,respectively.

In this configuration, although the amplitude of real and imaginary partsignals are not normalized, the imbalance of the real and imaginary partsignals is compensated for. Therefore, in a receiver for demodulatingoptical signals according to a ratio between the real and imaginary partsignals I and Q, even this configuration precisely recovers transmissiondata.

Variation 2 of Third Embodiment

The digital coherent optical receiver in the third embodiment, as in thefirst or second embodiment, does not need an I-Q amplitude errorcompensation circuit. In this case, I₁, Q₁, I₁ ² and Q₁ ² are input tothe I-Q amplitude error compensation circuit for each symbol. Anintegration circuit 99 illustrated in FIG. 11 has functionscorresponding to the averaging circuit 86, the multiplier 87, and theaccumulation adder 88.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiment (s) of the presentinventions has(have) been described in detail, it should be understoodthat the various changes, substitutions, and alterations could be madehereto without departing from the spirit and scope of the invention.

1. A digital coherent optical receiver provided with a 90-degree opticalhybrid circuit for detecting an in-phase signal and a quadrature signalof an input optical signal, comprising: a first circuit to calculate asquare of a sum of the in-phase signal and the quadrature signal; asecond circuit to subtract a squared value of the in-phase signal and asquared value of the quadrature signal from the calculation result ofthe first circuit; a third circuit to detect a phase error of the90-degree optical hybrid circuit based on the calculation result of thesecond circuit; and a fourth circuit to correct at least one of thein-phase signal and the quadrature signal according to the phase errordetected by the third circuit.
 2. The digital coherent optical receiveraccording to claim 1, wherein the phase error of the 90-degree opticalhybrid circuit is expressed by θ, and wherein the third circuitcalculates sin θ based on the calculation result of the second circuit,and the fourth circuit comprises a fifth circuit to calculate cos θ fromthe sin θ; a sixth circuit to correct the in-phase signal using the cosθ; and a seventh circuit to correct the quadrature signal using aproduct of the in-phase signal and the sin θ.
 3. The digital coherentoptical receiver according to claim 1, further comprising an additioncircuit to calculate a sum of a squared value of the in-phase signal anda squared value of the quadrature signal, wherein the second circuitsubtracts the calculation result of the addition circuit from thecalculation result of the first circuit.
 4. A digital coherent opticalreceiver provided with a 90-degree optical hybrid circuit for detectingan in-phase signal and a quadrature signal of an input optical signal,comprising: an amplitude error compensation circuit to generate a secondin-phase signal by correcting the in-phase signal in such a way thatamplitude information about the in-phase signal coincides with a targetvalue and generate a second quadrature signal by correcting thequadrature signal in such a way that amplitude information about thequadrature signal coincides with the target value; a first circuit tocalculate a square of a sum of the second in-phase signal and the secondquadrature signal; a second circuit to subtract a squared value of thesecond in-phase signal and a squared value of the second quadraturesignal from the calculation result of the first circuit; a third circuitto detect a phase error of the 90-degree optical hybrid circuit based onthe calculation result of the second circuit; and a fourth circuit tocorrect at least one of the second in-phase signal and the secondquadrature signal according to the phase error detected by the thirdcircuit.
 5. The digital coherent optical receiver according to claim 4,wherein the phase error of the 90-degree optical hybrid circuit isexpressed by θ, and wherein the third circuit calculates sin θ based onthe calculation result of the second circuit, and the fourth circuitcomprises a fifth circuit to calculate cos θ from the sin θ; a sixthcircuit to correct the second in-phase signal using the cos θ; and aseventh circuit to correct the second quadrature signal using a productof the second in-phase signal and the sin θ.
 6. The digital coherentoptical receiver according to claim 4, wherein the target value is 2^(N)where N is a integer, the amplitude error compensation circuit correctsthe in-phase signal and the quadrature signal in such a way that each ofan average of a square of the in-phase signal and an average of a squareof the quadrature signal coincides with the target value, and the thirdcircuit comprises a first divider to divide the calculation result ofthe second circuit by 2; an averaging circuit to average an outputsignal of the first divider; and a second divider to detect the phaseerror by dividing the output signal of the averaging circuit by thetarget value.
 7. The digital coherent optical receiver according toclaim 6, wherein each of the first and second dividers is a bit shiftcircuit.
 8. The digital coherent optical receiver according to claim 4,wherein the target value is 1, the amplitude error compensation circuitcorrects the in-phase signal and the quadrature signal in such a waythat each of an average of a square of the in-phase signal and anaverage of a square of the quadrature signal coincides with the targetvalue, and the third circuit comprises a divider to divide thecalculation result of the second circuit by 2; and an averaging circuitto detect the phase error by averaging the output signal of the divider.9. The digital coherent optical receiver according to claim 8, whereinthe divider is a bit shift circuit.
 10. A digital coherent opticalreceiver provided with a 90-degree optical hybrid circuit for detectingan in-phase signal and a quadrature signal of an input optical signal,comprising: a phase error compensation circuit to generate a firstsignal and a second signal, which represent the in-phase signal and thequadrature signal whose phase error of the 90-degree optical hybridcircuit is compensated for, according to the in-phase signal and thequadrature signal, wherein the phase error compensation circuitcomprises a first calculation circuit to calculate a square of a sum ofthe first signal and the second signal; a second circuit to subtract asquared value of the first signal and a squared value of the secondsignal from the calculation result of the first circuit; a third circuitto detect the phase error of the 90-degree optical hybrid circuit basedon the calculation result of the second circuit; and a fourth circuit togenerate the first signal and the second signal by correcting at leastone of the in-phase signal and the quadrature signal according to thephase error detected by the third circuit.